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"Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias."

Breeta SenGupta, Urban Ingelsson, Erik Larsson (2012)

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DOI: 10.1109/VLSID.2012.111

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/SenGuptaIL12
Breeta SenGupta, Urban Ingelsson, Erik Larsson:
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. VLSI Design 2012: 442-447

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