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"A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate ..."

Rajiv V. Joshi et al. (2007)

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DOI: 10.1109/VLSID.2007.182

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vlsid/JoshiKWNC07
Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang:
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design 2007: 665-672

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