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"Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with ..."

Yi-Chun Shih et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502260

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-07

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  - conf/vlsic/ShihLCLLCLYYCCC18
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  - https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18
Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. VLSI Circuits 2018: 79-80

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