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"An analytical placer for heterogeneous FPGAs via rough-placed packing."

Wan-Ning Wu et al. (2017)

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DOI: 10.1109/VLSI-DAT.2017.7939659

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-20

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  - conf/vlsi-dat/WuCCWC17
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  - https://dblp.org/rec/conf/vlsi-dat/WuCCWC17
Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen:
An analytical placer for heterogeneous FPGAs via rough-placed packing. VLSI-DAT 2017: 1-4

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