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"High-speed and low-power VLSI-architecture for inexact speculative adder."

Rahul Shrestha (2017)

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DOI: 10.1109/VLSI-DAT.2017.7939644

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-20

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Rahul Shrestha:
High-speed and low-power VLSI-architecture for inexact speculative adder. VLSI-DAT 2017: 1-4

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