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"A High-Performance VLSI Architecture of the Present Cipher and its ..."

Jai Gopal Pandey et al. (2018)

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DOI: 10.1109/SOCC.2018.8618487

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  - conf/socc/PandeyGNMKS18
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Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Abhijit Karmakar, Raj Singh:
A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs. SoCC 2018: 96-101

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