Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Power-Silicon Efficient All-Digital △Σ TDC with Differential ..."

Parth Parekh, Fei Yuan (2018)

> Home

Details and statistics

DOI: 10.1109/NEWCAS.2018.8585621

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/newcas/ParekhY18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/newcas/ParekhY18
Parth Parekh, Fei Yuan:
Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. NEWCAS 2018: 191-194

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.