"DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs."

Osamu Hirabayashi et al. (2002)

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DOI: 10.1109/TEST.2002.1041757

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka:
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ITC 2002: 164-169

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