"25-Gb/s clock and data recovery IC using latch-load combined with CML ..."

Tomonori Tanaka et al. (2017)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2017.8050696

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/TanakaFUNKAOIKN17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/TanakaFUNKAOIKN17
Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka:
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ISCAS 2017: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.