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"A 32×24-bit multiplier-accumulator with advanced rectangular styled ..."

Niichi Itoh et al. (2005)

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DOI: 10.1109/ISCAS.2005.1464527

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/iscas/ItohTSNTM05
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Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino:
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) 2005: 73-76

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