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"Chip-level characterization and RTN-induced error mitigation beyond 20nm ..."
T. W. Lin et al. (2018)
- T. W. Lin, S. H. Ku, C. H. Cheng, C. W. Lee, Ijen Huang, Wen-Jer Tsai, T. C. Lu, W. P. Lu, K. C. Chen, Tahui Wang, Chih-Yuan Lu:
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. IRPS 2018: 6-1
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