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"Stratix™ 10 High Performance Routable Clock Networks."

Carl Ebeling et al. (2016)

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DOI: 10.1145/2847263.2847279

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-01

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  dblp key:
  - conf/fpga/EbelingHLS16
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  - https://dblp.org/rec/conf/fpga/EbelingHLS16
Carl Ebeling, Dana How, David M. Lewis, Herman Schmit:
Stratix™ 10 High Performance Routable Clock Networks. FPGA 2016: 64-73

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