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"Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld ..."

Carlos Flores Fajardo et al. (2011)

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DOI: 10.1145/2024724.2024938

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-15

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  - conf/dac/FajardoFIGLZ11
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Carlos Flores Fajardo, Zhen Fang, Ravi R. Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao:
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. DAC 2011: 966-971

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