"A 512-KB level-2 cache design in 45-nm for low power IA processor ..."

Mohammed H. Taufique et al. (2008)

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DOI: 10.1109/CICC.2008.4672105

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Mohammed H. Taufique, Alex Okpisz, Haseeb N. Ahmed, John R. Riley, Mohammad M. Hasan, Gianfranco Gerosa:
A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne. CICC 2008: 403-406

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