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"A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS."

Joseph F. Ryan, Benton H. Calhoun (2010)

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DOI: 10.1109/CICC.2010.5617466

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Joseph F. Ryan, Benton H. Calhoun:
A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. CICC 2010: 1-4

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