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"A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with ..."

Shuai Chen et al. (2013)

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DOI: 10.1109/CICC.2013.6658549

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-21

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Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang:
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. CICC 2013: 1-4

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