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"An Efficient FPGA Accelerator Design for Optimized CNNs Using OpenCL."

Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele (2019)

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DOI: 10.1007/978-3-030-18656-2_18

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-14

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  dblp key:
  - conf/arcs/VemparalaFS19
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  - https://dblp.org/rec/conf/arcs/VemparalaFS19
Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele:
An Efficient FPGA Accelerator Design for Optimized CNNs Using OpenCL. ARCS 2019: 236-249

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