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"A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a ..."

Ki-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi (2016)

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DOI: 10.1109/APCCAS.2016.7803966

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Ki-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi:
A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. APCCAS 2016: 327-329

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