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Raymond R. Hoare
Person information
- affiliation: University of Pittsburgh, Pennsylvania, USA
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2010 – 2019
- 2014
- [c30]Raymond R. Hoare, Denis Smetana:
Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools. HPEC 2014: 1-6
2000 – 2009
- 2008
- [j12]Raymond R. Hoare, Zhu Ding, Alex K. Jones
:
A two-stage hardware scheduler combining greedy and optimal scheduling. J. Parallel Distributed Comput. 68(11): 1437-1451 (2008) - [j11]Alex K. Jones
, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak
, Raymond R. Hoare, James T. Cain, Marlin H. Mickle:
Radio frequency identification prototyping. ACM Trans. Design Autom. Electr. Syst. 13(2): 29:1-29:22 (2008) - [c29]Ying Yu, Raymond R. Hoare, Alex K. Jones
:
A CAM-based intrusion detection system for single-packet attack detection. IPDPS 2008: 1-8 - 2007
- [j10]Alex K. Jones
, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle:
An automated, FPGA-based reconfigurable, low-power RFID tag. Microprocess. Microsystems 31(2): 116-134 (2007) - [c28]Alex K. Jones
, Raymond R. Hoare, Joseph St. Onge, Joshua M. Lucas, Shuyi Shao, Rami G. Melhem:
Linking Compilation and Visualization for Massively Parallel Programs. IPDPS 2007: 1-8 - 2006
- [j9]Raymond R. Hoare, Alex K. Jones
, Dara Kusic
, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud:
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions. EURASIP J. Adv. Signal Process. 2006 (2006) - [j8]Jeffrey William Schuster, Kshitij Gupta, Raymond Hoare, Alex K. Jones
:
Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition. EURASIP J. Embed. Syst. 2006 (2006) - [j7]Alex K. Jones
, Swapna R. Dontharaju, Shen Chih Tung, Peter J. Hawrylak, Leonid Mats, Raymond R. Hoare, James T. Cain, Marlin H. Mickle:
Passive active radio frequency identification tags. Int. J. Radio Freq. Identif. Technol. Appl. 1(1): 52-73 (2006) - [j6]Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones:
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. J. Low Power Electron. 2(2): 148-164 (2006) - [j5]Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
:
Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocess. Microsystems 30(7): 445-456 (2006) - [j4]Alex K. Jones
, Raymond R. Hoare, Dara Kusic
, Justin Stander, Gayatri Mehta, Joshua Fazekas:
A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1250-1254 (2006) - [j3]Alex K. Jones
, Raymond Hoare, Dara Kusic
, Gayatri Mehta, Joshua Fazekas, John Foster:
Reducing power while increasing performance with supercisc. ACM Trans. Embed. Comput. Syst. 5(3): 658-686 (2006) - [c27]Alex K. Jones
, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle:
An automated, reconfigurable, low-power RFID tag. DAC 2006: 131-136 - [c26]Alex K. Jones
, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle:
A Field Programmable RFID Tag and Associated Design Flow. FCCM 2006: 165-174 - [c25]Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
:
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM 2006: 299-300 - [c24]Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
:
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. FCCM 2006: 309-310 - [c23]Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
:
Design space exploration for low-power reconfigurable fabrics. IPDPS 2006 - [c22]Jeffrey William Schuster, Kshitij Gupta, Raymond R. Hoare:
Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition. IPDPS 2006 - [c21]Ying Yu, Raymond R. Hoare, Alex K. Jones, Ralph Sprang:
A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. ISCAS 2006 - [c20]Raymond R. Hoare, Zhu Ding, Alex K. Jones
:
Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. SC 2006: 94 - [c19]Zhu Ding, Raymond R. Hoare, Alex K. Jones
, Rami G. Melhem:
Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks. SC 2006: 96 - 2005
- [j2]Raymond R. Hoare, Zhu Ding, Shen Chih Tung, Rami G. Melhem, Alex K. Jones
:
A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. J. Parallel Distributed Comput. 65(10): 1237-1252 (2005) - [c18]Joshua M. Lucas, Raymond Hoare, Alex K. Jones
:
Optimizing Technology Mapping for FPGAs Using CAMs. FCCM 2005: 293-294 - [c17]Alex K. Jones
, Raymond Hoare, Dara Kusic
, Joshua Fazekas, John Foster:
An FPGA-based VLIW processor with custom hardware execution. FPGA 2005: 107-117 - [c16]Zhu Ding, Raymond R. Hoare, Alex K. Jones
, Dan Li, Shou-Kuo Shao, Shen-Chien Tung, Jiang Zheng, Rami G. Melhem:
Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. IPDPS 2005 - [c15]Dara Kusic
, Raymond Hoare, Alex K. Jones
, Joshua Fazekas, John Foster:
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. IPDPS 2005 - [c14]Kevin J. Barker
, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones
, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker:
On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. SC 2005: 16 - 2004
- [c13]Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh:
A 64-way VLIW/SIMD FPGA architecture and design flow. ICECS 2004: 499-502 - [c12]Joshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones:
LURU: global-scope FPGA technology mapping with content-addressable memories. ICECS 2004: 599-602 - [c11]Raymond Hoare, Shen Chih Tung, Katrina Werger:
An 88-Way Multiprocessor within an FPGA with Customizable Instructions. IPDPS 2004 - 2003
- [c10]Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis:
Short Courses in System-on-a-Chip (SoC) Design. MSE 2003: 126-127 - [c9]Raymond Hoare, Shen Chih Tung:
Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity? MSE 2003: 128-130 - 2002
- [j1]Raymond Hoare, Mary Besterfield-Sacre
, Dan Ertman, Jessica Gerchak, Troy A. Johnson, Robert Shields, Larry J. Shuman:
Cross-institutional assessment: Development and implementation of the On-line Student Survey System. Comput. Appl. Eng. Educ. 10(2): 88-97 (2002) - [c8]David Reed, Raymond Hoare:
An SoC Solution for Massive Parallel Processing. IPDPS 2002 - [c7]Raymond R. Hoare, D. Swope, S. Bailey:
A Width Expansion of MMX/SIMD Processing Architecture on an FPGA. IASTED PDCS 2002: 562-566 - 2001
- [c6]Troy A. Johnson, Raymond R. Hoare:
Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor Systems. IPDPS 2001: 193 - 2000
- [c5]Raymond Hoare:
ClusterNet: An Object-Oriented Cluster Network. IPDPS Workshops 2000: 28-38
1990 – 1999
- 1998
- [c4]Raymond Hoare, Henry G. Dietz:
A Case for Aggregate Networks. IPPS/SPDP 1998: 162-166 - 1997
- [c3]Soohong P. Kim, Raymond Hoare, Henry G. Dietz:
VLIW Across Multiple Superscalar Processors on a Single Chip. IEEE PACT 1997: 166- - 1996
- [c2]Henry G. Dietz, Raymond Hoare, Timothy Mattox:
A Fine-Grain Parallel Architecture Based on Barrier Synchronization. ICPP, Vol. 1 1996: 247-250 - [c1]Raymond Hoare, Henry G. Dietz, Timothy Mattox, Soohong P. Kim:
Bitwise aggregate networks. SPDP 1996: 306-313
Coauthor Index
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