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2000 – 2009
- 2009
[j10]Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi:
A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control. IEICE Electron. Express 6(8): 456-460 (2009)- 2008
- [j9]Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa:
Delayed-ABC SOI for crosstalk noise repair. IEICE Electron. Express 5(9): 354-360 (2008) - [j8]Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation. J. Comput. 3(5): 34-40 (2008) - 2007
- [j7]Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa:
Charge recycling in MTCMOS circuits with block dividing. IEICE Electron. Express 4(18): 562-568 (2007) - [j6]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa:
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation. IEICE Trans. Electron. 90-C(4): 666-674 (2007) - [j5]Fukashi Morishita
, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. 90-C(4): 765-771 (2007) - [j4]Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2691-2694 (2007) - [j3]Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto:
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42(4): 853-861 (2007) - [j2]Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi:
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42(11): 2611-2619 (2007) - [c4]Mitsuo Usami, Hisao Tanabe, Akira Sato, Isao Sakama, Yukio Maki, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue:
A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory. ISSCC 2007: 482-483 - [c3]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. VLSI Design 2007: 609-614 - 2006
- [j1]Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI. IEICE Electron. Express 3(21): 453-458 (2006) - [c2]Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka:
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC 2006: 429-432 - 2005
- [c1]Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC 2005: 435-438
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