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Daehyun Kim 0001
Person information
- affiliation: Intel Corporation, Santa Clara, CA, USA
Other persons with the same name
- Daehyun Kim (aka: Dae Hyun Kim, Dae-Hyun Kim) — disambiguation page
- Daehyun Kim 0002 — Georgia Institute of Technology, GA, USA
- Dae-Hyun Kim 0003 (aka: Dae Hyun Kim 0003, Daehyun Kim 0003) — Samsung Electronics, Hwaseong, Korea (and 1 more)
- Dae Hyun Kim 0004 (aka: Dae-Hyun Kim 0004, Daehyun Kim 0004) — Washington State University (WSU), School of Electrical Engineering and Computer Science, Pullman, WA, USA (and 1 more)
- Daehyun Kim 0005 (aka: Dae Hyun Kim 0005) — KAIST, Korea (and 1 more)
- Daehyun Kim 0006 (aka: Dae Hyun Kim 0006) — University of Illinois at Urbana-Champaign, Department of Aerospace Engineering, IL, USA
- Daehyun Kim 0007 — UCLA, Department of Economics Los Angeles, CA, USA
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2010 – 2019
- 2014
- [c16]Karthikeyan Vaidyanathan, Kiran Pamnany, Dhiraj D. Kalamkar, Alexander Heinecke, Mikhail Smelyanskiy, Jongsoo Park, Daehyun Kim, Aniruddha G. Shet, Bharat Kaul, Bálint Joó, Pradeep Dubey:
Improving Communication Performance and Scalability of Native Applications on Intel Xeon Phi Coprocessor Clusters. IPDPS 2014: 1083-1092 - 2013
- [j8]Jongsoo Park, Ping Tak Peter Tang, Mikhail Smelyanskiy, Daehyun Kim, Thomas Benson:
Efficient backprojection-based synthetic aperture radar computation with many-core processors. Sci. Program. 21(3-4): 165-179 (2013) - [j7]Ping Tak Peter Tang, Jongsoo Park, Daehyun Kim, Vladimir Petrov:
A framework for low-communication 1-D FFT. Sci. Program. 21(3-4): 181-195 (2013) - [c15]Jongsoo Park, Richard M. Yoo, Daya Shanker Khudia, Christopher J. Hughes, Daehyun Kim:
Location-aware cache management for many-core processors with deep cache hierarchy. SC 2013: 20:1-20:12 - [c14]Jongsoo Park, Ganesh Bikshandi, Karthikeyan Vaidyanathan, Ping Tak Peter Tang, Pradeep Dubey, Daehyun Kim:
Tera-scale 1D FFT with low-communication algorithm and Intel® Xeon Phi™ coprocessors. SC 2013: 34:1-34:12 - 2012
- [c13]Dongki Kim, Sungkwang Lee, Jaewoong Chung, Daehyun Kim, Dong Hyuk Woo, Sungjoo Yoo, Sunggu Lee:
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU. DAC 2012: 888-896 - [c12]Dhiraj D. Kalamkar, Joshua D. Trzasko, Srinivas Sridharan, Mikhail Smelyanskiy, Daehyun Kim, Armando Manduca, Yunhong Shu, Matt A. Bernstein, Bharat Kaul, Pradeep Dubey:
High Performance Non-uniform FFT on Modern X86-based Multi-core Systems. IPDPS 2012: 449-460 - [c11]Jongsoo Park, Ping Tak Peter Tang, Mikhail Smelyanskiy, Daehyun Kim, Thomas Benson:
Efficient backprojection-based synthetic aperture radar computation with many-core processors. SC 2012: 28 - [c10]Ping Tak Peter Tang, Jongsoo Park, Daehyun Kim, Vladimir Petrov:
A framework for low-communication 1-D FFT. SC 2012: 42 - 2011
- [j6]Daehyun Kim, Joshua Trzasko, Mikhail Smelyanskiy, Clifton Haider, Pradeep Dubey, Armando Manduca:
High-Performance 3D Compressive Sensing MRI Reconstruction Using Many-Core Architectures. Int. J. Biomed. Imaging 2011: 473128:1-473128:11 (2011) - 2010
- [j5]Daehyun Kim, Victor W. Lee, Yen-Kuang Chen:
Image Processing on Multicore x86 Architectures. IEEE Signal Process. Mag. 27(2): 97-107 (2010) - [c9]Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey:
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. ISCA 2010: 451-460 - [c8]Nadathur Satish, Changkyu Kim, Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, Daehyun Kim, Pradeep Dubey:
Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. SIGMOD Conference 2010: 351-362
2000 – 2009
- 2009
- [j4]Mikhail Smelyanskiy, David R. Holmes III, Jatin Chhugani, Alan Larson, Doug Carmean, Dennis P. Hanson, Pradeep Dubey, Kurt Augustine, Daehyun Kim, Alan Kyker, Victor W. Lee, Anthony D. Nguyen, Larry Seiler, Richard A. Robb:
Mapping High-Fidelity Volume Rendering for Medical Imaging to CPU, GPU and Many-Core Architectures. IEEE Trans. Vis. Comput. Graph. 15(6): 1563-1570 (2009) - 2008
- [j3]Sanjeev Kumar, Jatin Chhugani, Changkyu Kim, Daehyun Kim, Anthony D. Nguyen, Pradeep Dubey, Christian Bienia, Youngmin Kim:
Second Life and the New Generation of Virtual Worlds. Computer 41(9): 46-53 (2008) - [j2]Yen-Kuang Chen, Jatin Chhugani, Pradeep Dubey, Christopher J. Hughes, Daehyun Kim, Sanjeev Kumar, Victor W. Lee, Anthony D. Nguyen, Mikhail Smelyanskiy:
Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications. Proc. IEEE 96(5): 790-807 (2008) - [c7]Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen:
Atomic Vector Operations on Chip Multiprocessors. ISCA 2008: 441-452 - 2007
- [j1]Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony D. Nguyen, Yen-Kuang Chen, Pradeep Dubey:
Cache-conscious frequent pattern mining on modern and emerging processors. VLDB J. 16(1): 77-96 (2007) - [c6]Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen:
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. ISCA 2007: 220-231 - [c5]Mikhail Smelyanskiy, Victor W. Lee, Daehyun Kim, Anthony D. Nguyen, Pradeep Dubey:
Scaling performance of interior-point method on large-scale chip multiprocessor system. SC 2007: 22 - 2006
- [c4]Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim:
Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures. Memory System Performance and Correctness 2006: 31-40 - 2005
- [c3]Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee:
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. DAC 2005: 553-558 - [c2]Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony D. Nguyen, Yen-Kuang Chen, Pradeep Dubey:
A Characterization of Data Mining Workloads on a Modern Processor. DaMoN 2005 - [c1]Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony D. Nguyen, Yen-Kuang Chen, Pradeep Dubey:
Cache-conscious Frequent Pattern Mining on a Modern Processor. VLDB 2005: 577-588
Coauthor Index
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