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Arasu T. Senthil

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2000 – 2009

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2007
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Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy:
Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electron. 3(1): 106-118 (2007)
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M. Thenappan, Arasu T. Senthil, K. M. Sreekanth, Ramesh S. Guzar:
An Overlap Removal Algorithm for Macrocell Placement in VLSI Layouts. ICCTA 2007: 104-110
2005
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Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy:
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. ITC 2005: 9

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