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Yuri Stepchenkov

Yury Stepchenkov – Y. A. Stepchenkov

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2020 – today

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2022
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Igor Sokolov, Y. A. Stepchenkov, Yuri Rogdestvenski, Y. G. Diachenko:
Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems. Autom. Remote. Control. 83(2): 264-272 (2022)
2021
[c13]
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Yury Stepchenkov, Yury Diachenko, Yury Rogdestvenski, Yury Shikunov, Denis Diachenko:
Self-Timed Storage Register Soft Error Tolerance Improvement. EWDTS 2021: 1-6
[c12]
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Yury Stepchenkov, Dmitry Khilko, Yury Shikunov, Georgy Orlov:
Design Validation of Recurrent Signal Processor FPGA prototype. EWDTS 2021: 1-5
2020
[c11]
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Yuri Stepchenkov, Yuri Rogdestvenski, Anton N. Kamenskih, Yuri Diachenko, Denis Diachenko:
Improvement of the Quasi Delay-Insensitive Pipeline Noise Immunity. DESSERT 2020: 47-51
[c10]
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Igor Sokolov, Yuri Stepchenkov, Yuri Diachenko, Yuri Rogdestvenski, Denis Diachenko:
Increasing Self-Timed Circuit Soft Error Tolerance. EWDTS 2020: 1-5

2010 – 2019

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2019
[c9]
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Yuri Stepchenkov, Anton N. Kamenskih, Yuri Diachenko, Yuri Rogdestvenski, Denis Y. Diachenko:
Fault-Tolerance of Self-Timed Circuits. DESSERT 2019: 41-44
[c8]
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Dmitry Khilko, Yury Stepchenkov, Yury Shikunov, George Orlov:
Modeling and debugging tools development for recurrent architecture. EWDTS 2019: 1-5
[c7]
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Yuri Stepchenkov, Yuri Diachenko, Yuri Rogdestvenski, Yury Shikunov, Denis Diachenko:
Advanced Indication of the Self-Timed Circuits. EWDTS 2019: 1-6
2016
[c6]
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Yuri Stepchenkov, Victor N. Zakharov, Yuri Rogdestvenski, Yuri Diachenko, Nickolaj Morozov, Dmitri Stepchenkov:
Speed-independent fused multiply add and subtract unit. EWDTS 2016: 1-4
[c5]
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Yuri Stepchenkov, Dmitry Khilko, Yuri Diachenko, Yury Shikunov, Dimitry Shikunov:
Testing of software and hardware simulations of dataflow recurrent digital signal processor. EWDTS 2016: 1-4
2015
[c4]
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L. P. Plekhanov, Victor N. Zakharov, Y. A. Stepchenkov:
Functional approach in self-timed circuit design. EWDTS 2015: 1-6
[c3]
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Y. A. Stepchenkov, Victor N. Zakharov, Y. G. Diachenko, N. V. Morozov, D. Y. Stepchenkov:
Cell library for speed-independent VLSI. EWDTS 2015: 1-6
[c2]
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Y. A. Stepchenkov, Victor N. Zakharov, Y. V. Rogdestvenski, Y. G. Diachenko, N. V. Morozov, D. Y. Stepchenkov:
Speed-independent floating point coprocessor. EWDTS 2015: 1-6

2000 – 2009

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2009
[c1]
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Yuri Stepchenkov, Yuri Diachenko, Victor N. Zakharov, Yuri Rogdestvenski, Nikolai Morozov, Dmitri Stepchenkov:
Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation. PATMOS 2009: 276-285

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