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Yury Shikunov
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2020 – today
- 2021
- [c5]Yury Stepchenkov, Yury Diachenko, Yury Rogdestvenski, Yury Shikunov, Denis Diachenko:
Self-Timed Storage Register Soft Error Tolerance Improvement. EWDTS 2021: 1-6 - [c4]Yury Stepchenkov, Dmitry Khilko, Yury Shikunov, Georgy Orlov
:
Design Validation of Recurrent Signal Processor FPGA prototype. EWDTS 2021: 1-5
2010 – 2019
- 2019
- [c3]Dmitry Khilko
, Yury Stepchenkov, Yury Shikunov
, George Orlov
:
Modeling and debugging tools development for recurrent architecture. EWDTS 2019: 1-5 - [c2]Yuri Stepchenkov, Yuri Diachenko, Yuri Rogdestvenski, Yury Shikunov
, Denis Diachenko:
Advanced Indication of the Self-Timed Circuits. EWDTS 2019: 1-6 - 2016
- [c1]Yuri Stepchenkov, Dmitry Khilko
, Yuri Diachenko, Yury Shikunov
, Dimitry Shikunov:
Testing of software and hardware simulations of dataflow recurrent digital signal processor. EWDTS 2016: 1-4
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last updated on 2024-04-24 22:57 CEST by the dblp team
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