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Hideki Kano
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2010 – 2019
- 2016
- [c5]Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC 2016: 64-65 - [c4]Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [c3]Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Tomoyuki Arai, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS. A-SSCC 2015: 1-4 - 2014
- [j3]Kazuaki Oishi, Eiji Yoshida
, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. IEEE J. Solid State Circuits 49(12): 2915-2924 (2014) - [c2]Kazuaki Oishi, Eiji Yoshida
, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura
, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. ISSCC 2014: 60-61 - 2012
- [c1]Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura
:
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. ISSCC 2012: 86-88
2000 – 2009
- 2002
- [j2]Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe:
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology. IEEE J. Solid State Circuits 37(12): 1703-1709 (2002)
1990 – 1999
- 1998
- [j1]Satoshi Eto, Masato Matsumiya, Masato Takita, Yuki Ishii, Toshikazu Nakamura, Kuninori Kawabata, Hideki Kano, Ayako Kitamoto, Toshimi Ikeda, Toru Koga, Mitsuhiro Higashiho, Yuji Serizawa, Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Masao Taguchi:
A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line. IEEE J. Solid State Circuits 33(11): 1697-1702 (1998)
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