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K. Radhakrishna Rao
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Journal Articles
- 1988
- [j2]K. Radhakrishna Rao, Pranav Ashar:
Magnitude locked loop. Proc. IEEE 76(2): 201-203 (1988) - 1987
- [j1]K. Radhakrishna Rao, G. Venugopal:
A novel technique for the on-chip tuning of monolithic filters. Proc. IEEE 75(2): 257-258 (1987)
Conference and Workshop Papers
- 2006
- [c10]Saurabh Singh, K. Radhakrishna Rao:
Low Voltage Analogue Multiplier. APCCAS 2006: 1772-1775 - 2003
- [c9]Anantha Nag, K. Radhakrishna Rao:
Narrow Band Noise Suppression Scheme for improving Signal to Noise Ratio. VLSI Design 2003: 25-29 - [c8]J. Veerendra Kumar, K. Radhakrishna Rao:
A Low-Voltage Low Power CMOS Companding Filter. VLSI Design 2003: 309-314 - 2002
- [c7]J. Veerendra Kumar, K. Radhakrishna Rao:
A low-voltage low power square-root domain filter. APCCAS (2) 2002: 375-378 - 1998
- [c6]Srinivasan Venkatraman, Srikanth Natarajan, K. Radhakrishna Rao:
A Low Power Video Frequency Continuous Time Filter. VLSI Design 1998: 140-144 - [c5]Srinivasan Venkatraman, Srikanth Natarajan, K. Radhakrishna Rao:
A New Tuning Scheme for Continuous Time Filters. VLSI Design 1998: 150-154 - [c4]S. Pradeep Kiran, K. Radhakrishna Rao:
A Novel Translinear Principle Based BiMOS Transconductor. VLSI Design 1998: 161-166 - 1997
- [c3]K. Ravi Shankar, K. Radhakrishna Rao, Srinivasan Venkatraman:
Tuning Schemes for Transmission Zeros of Continuous-Time Filters. VLSI Design 1997: 435-438 - 1996
- [c2]C. Srinivasan, K. Radhakrishna Rao:
A 20MHz CMOS Variable Gain Amplifier. VLSI Design 1996: 90-93 - 1986
- [c1]Mohan Harihara, K. Radhakrishna Rao:
Mridangam Simulation. ICMC 1986
Coauthor Index
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