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Vicente Yair Ponce-Hinestroza

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Conference and Workshop Papers

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2018
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Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz:
System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog^®=-AMS. SMACD 2018: 301-304
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Alejandro Garcia-Santiago, Josefina Castañeda-Camacho, José-Fermi Guerrero-Castellanos, Gerardo Mino Aguilar, Vicente Yair Ponce-Hinestroza:
Simulation Platform for a VANET Using the TrueTime Toolbox: Further Result Toward Cyber-Physical Vehicle Systems. VTC Fall 2018: 1-5
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Vicente Yair Ponce-Hinestroza, Josefina Castañeda-Camacho, Victor R. Gonzalez-Diaz, Gerardo Mino Aguilar, Alejandro Garcia-Santiago:
Pipeline A/D Converter Design for 5G OFDM Communications Systems. VTC Fall 2018: 1-5

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