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Sreenivasulu Polineni
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Journal Articles
- 2021
- [j4]Sreenivasulu Polineni, S. Rekha, M. S. Bhat:
A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications. IET Circuits Devices Syst. 15(2): 141-155 (2021) - 2020
- [j3]Sreenivasulu Polineni, M. S. Bhat, S. Rekha:
A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique. Circuits Syst. Signal Process. 39(11): 5352-5370 (2020) - [j2]G. Hanumantha Rao, Sreenivasulu Polineni, S. Rekha, M. S. Bhat:
A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing. Int. J. Circuit Theory Appl. 48(11): 1853-1863 (2020) - 2019
- [j1]Sreenivasulu Polineni, G. Hanumanta Rao, S. Rekha, M. S. Bhat:
A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system. Microelectron. J. 94 (2019)
Conference and Workshop Papers
- 2019
- [c2]Samarth Bonthala, Yashas Uppoor, Ashika Nayak, Sreenivasulu Polineni, M. S. Bhat:
Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology. ISED 2019: 1-6 - 2018
- [c1]M. K. Jayaram Reddy, Sreenivasulu Polineni, Laxminidhi Tonse:
91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical Applications. ISVLSI 2018: 453-457
Coauthor Index
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