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2020 – today
- 2023
[c5]Feng-Hsiag Hsiao, Po-Wei Chiu, Shou-Wen Chang:
Integrating RC6 Stream Cipher to A Chaotic Synchronization System. SmartCloud 2023: 86-88- 2022
- [j3]Po-Wei Chiu
, Chris H. Kim:
A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1943-1951 (2022) - 2021
- [j2]Ibrahim Ahmed, Po-Wei Chiu, William Moy, Chris H. Kim:
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits 56(9): 2870-2880 (2021) - 2020
- [c4]Po-Wei Chiu, Chris H. Kim:
22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor. ISSCC 2020: 336-338 - [c3]Ibrahim Ahmed, Po-Wei Chiu, Chris H. Kim:
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c2]Gyusung Park, Minsu Kim, Nakul Pande, Po-Wei Chiu, Jeehwan Song, Chris H. Kim:
A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing. CICC 2019: 1-4 - 2018
- [j1]Po-Wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim:
A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer. IEEE J. Solid State Circuits 53(4): 1203-1213 (2018) - [c1]Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim:
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. A-SSCC 2018: 187-190
Coauthor Index
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