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Journal Articles
- 2021
[j3]Biruk B. Seyoum
, Marco Pagani, Alessandro Biondi, Sara Balleri, Giorgio C. Buttazzo:
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs. IEEE Trans. Computers 70(11): 1988-2000 (2021)- 2019
- [j2]Biruk B. Seyoum, Alessandro Biondi, Giorgio C. Buttazzo:
FLORA: FLoorplan Optimizer for Reconfigurable Areas in FPGAs. ACM Trans. Embed. Comput. Syst. 18(5s): 73:1-73:20 (2019) - 2017
- [j1]Biruk B. Seyoum, Maurizio Rossi, Davide Brunelli:
Energy Neutral Wireless Bolt for Safety Critical Fastening. Sensors 17(10): 2211 (2017)
Conference and Workshop Papers
- 2023
- [c6]Kuan-Lin Chiu, Guy Eichler, Biruk B. Seyoum, Luca P. Carloni:
EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators. CPS-IoT Week Workshops 2023: 209-214 - [c5]Biruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter, Luca P. Carloni:
PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs. DATE 2023: 1-6 - [c4]Guy Eichler, Biruk B. Seyoum, Kuan-Lin Chiu, Luca P. Carloni:
MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain-Computer Interfaces. ICCD 2023: 70-77 - 2022
- [c3]Biruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, Luca P. Carloni:
Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs. CASES 2022: 25-26 - 2021
- [c2]Biruk B. Seyoum, Marco Pagani, Alessandro Biondi, Giorgio C. Buttazzo:
Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC. SAC 2021: 481-490 - 2017
- [c1]Biruk B. Seyoum, Maurizio Rossi, Davide Brunelli:
A self-powered wireless bolt for smart critical fastener. GIoTS 2017: 1-6
Coauthor Index
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