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Xianshan Wen
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2020 – today
- 2024
- [j3]Xianshan Wen
, Tao Fu
, Liang Fang
, Ping Gui
:
A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS. IEEE Access 12: 36951-36960 (2024) - 2022
- [j2]Liang Fang
, Xianshan Wen
, Tao Fu
, Ping Gui
:
A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3225-3236 (2022) - [j1]Liang Fang
, Xianshan Wen, Tao Fu
, Guanhua Wang
, Sandeep Miryala, Tiehui Ted Liu, Ping Gui:
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 123-133 (2022) - [c3]Xianshan Wen, Ruobing Hua, Jianye Liu, Tao Fu, Liang Fang, Xiaoran Wang, Mitchell A. Thornton, Ping Gui:
Controller Area Network (CAN) Bus Transceiver with Authentication Support. ISCAS 2022: 1328-1331 - 2021
- [c2]Liang Fang, Tao Fu, Xianshan Wen, Ping Gui:
A 1GS/s 82dB Peak-SFDR 12b Single-Channel Pipe-SAR ADC with Harmonic-Injecting Cross-Coupled-Pair and Fast N-replica Bootstrap Switch Achieving 7.5fj/conv-step. CICC 2021: 1-2
2010 – 2019
- 2017
- [c1]Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello:
Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. FPL 2017: 1-4
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last updated on 2024-04-24 23:16 CEST by the dblp team
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