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Tiankai Su
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2020 – today
- 2023
- [c9]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Divider Circuits by Hardware Reduction. SMACD 2023: 1-4 - 2020
- [j1]Maciej J. Ciesielski
, Tiankai Su, Atif Yasin
, Cunxi Yu
:
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1346-1357 (2020) - [c8]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE 2020: 532-537 - [c7]Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI 2020: 386-391
2010 – 2019
- 2019
- [c6]Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral approach to verifying non-linear arithmetic circuits. ASP-DAC 2019: 261-267 - [c5]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Integer Dividers: Division by a Constant. ISVLSI 2019: 76-81 - [c4]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC 2019: 257-262 - [i1]Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral Approach to Verifying Non-linear Arithmetic Circuits. CoRR abs/1901.02950 (2019) - 2018
- [c3]Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski:
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. ISCAS 2018: 1-5 - [c2]Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski:
Rewriting Environment for Arithmetic Circuit Verification. LPAR 2018: 656-666 - 2017
- [c1]Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski:
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. ISVLSI 2017: 415-420
Coauthor Index
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last updated on 2024-04-24 22:47 CEST by the dblp team
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