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ORCIDRajendra Kumar Nagaria
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2020 – today
- 2023
[j18]Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria, Deepak Gupta, Achyut Mani Tripathi, Om Jee Pandey:
Anchor-based void detouring routing protocol in three dimensional IoT networks. Comput. Networks 227: 109691 (2023)- [j17]Ankur Kumar, Rajendra Kumar Nagaria:
Reduction of variation and leakage in wide fan-in OR Logic domino gate. Integr. 89: 229-240 (2023) - 2022
- [j16]Ankur Kumar
, Rajendra Kumar Nagaria:
A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic. J. Circuits Syst. Comput. 31(3): 2250055:1-2250055:29 (2022) - 2021
- [j15]Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria, Deepak Gupta:
An Angular 3D Path Selection Protocol in Wireless Sensor Networks. Open Comput. Sci. 11(1): 190-207 (2021) - [j14]Vikrant Varshney, Avaneesh K. Dubey, Rajendra Kumar Nagaria:
Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications. J. Circuits Syst. Comput. 30(11): 2150191:1-2150191:22 (2021) - 2020
- [j13]Pratosh Kumar Pal, Rajendra Kumar Nagaria:
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load. Integr. 71: 115-124 (2020) - [j12]Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria:
3D geographical routing protocols in wireless ad hoc and sensor networks: an overview. Wirel. Networks 26(4): 2549-2566 (2020) - [c4]Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria:
Anchor Based Geographical Routing in WSN. ICSCA 2020: 222-226
2010 – 2019
- 2019
- [j11]Avaneesh K. Dubey, Rajendra Kumar Nagaria:
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect. J. Circuits Syst. Comput. 28(9): 1950157:1-1950157:18 (2019) - [j10]Pratosh Kumar Pal, Rajendra Kumar Nagaria:
A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body Biasing. J. Circuits Syst. Comput. 28(13): 1950215:1-1950215:22 (2019) - [c3]Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria:
Energy Efficient Angle based Route Selection in 3D Wireless Sensor Networks. SICE 2019: 388-393 - 2018
- [j9]Ankur Kumar, Rajendra Kumar Nagaria:
A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits. Integr. 63: 174-184 (2018) - [j8]Avaneesh K. Dubey, Rajendra Kumar Nagaria:
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique. J. Circuits Syst. Comput. 27(13): 1850204:1-1850204:17 (2018) - [j7]Avaneesh K. Dubey, Rajendra Kumar Nagaria:
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load. Microelectron. J. 78: 1-10 (2018) - [j6]Sankit R. Kassa, Rajendra Kumar Nagaria, R. Karthik:
Energy efficient neoteric design of a 3-input Majority Gate with its implementation and physical proof in Quantum dot Cellular Automata. Nano Commun. Networks 15: 28-40 (2018) - 2017
- [j5]Sankit R. Kassa, Rajendra Kumar Nagaria:
A Novel Design for 4-Bit Code Converters in Quantum Dot Cellular Automata. J. Low Power Electron. 13(3): 482-489 (2017) - 2016
- [j4]Sankit R. Kassa, Rajendra Kumar Nagaria:
An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata. J. Low Power Electron. 12(2): 107-111 (2016) - 2015
- [c2]Sankit R. Kassa, Rajendra Kumar Nagaria:
A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies. ICCCT 2015: 371-375 - 2013
- [j3]Shipra Upadhyay, Rajendra Kumar Nagaria, Ram Awadh Mishra:
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic. VLSI Design 2013: 726324:1-726324:9 (2013) - 2012
- [j2]Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari:
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. VLSI Design 2012: 173079:1-173079:18 (2012) - 2010
- [j1]Rajendra Kumar Nagaria, Rakesh Kumar Singh, Subodh Wairya:
On the New Design of sinusoid voltage Controlled oscillators Using Multiplier in CFA-Based Double Integrator Loop. J. Circuits Syst. Comput. 19(5): 939-948 (2010)
2000 – 2009
- 2009
- [c1]Pankaj Kumar Sharma, Rajendra Kumar Nagaria, T. N. Sharma:
PAPR Reduction for OFDM Scheme by New Partial Transmit Sequence Technique in Wireless Communication Systems. CICSyN 2009: 114-118
Coauthor Index
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