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ORCIDIyad Ouaiss
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Journal Articles
- 2020
[j6]Mohammad Al-Abbas
, Wissam Fawaz, Raymond Ghajar, Chadi Abou-Rjeily, Iyad Ouaiss, Zahi Nakad, George E. Nasr, Samer S. Saab:
Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism Course. IEEE Trans. Educ. 63(4): 273-282 (2020)- 2015
- [j5]Grace Zgheib, Iyad Ouaiss:
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations. J. Circuits Syst. Comput. 24(3): 1550039:1-1550039:19 (2015) - 2011
- [j4]Elie Elaaraj, Iyad Ouaiss:
A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis. J. Circuits Syst. Comput. 20(5): 943-973 (2011) - [j3]Maria Abi Saad, Iyad Ouaiss:
Priority-Driven Area Optimization in High-Level Synthesis. J. Circuits Syst. Comput. 20(6): 1131-1163 (2011) - 2010
- [j2]Wissam Fawaz, Iyad Ouaiss, Ken Chen, Harry G. Perros:
Deadline-based connection setup in wavelength-routed WDM networks. Comput. Networks 54(11): 1792-1804 (2010) - [j1]Samer S. Saab, Jad G. Hobeika, Iyad Ouaiss:
A novel pseudorandom noise and band jammer generator using a composite sinusoidal function. IEEE Trans. Signal Process. 58(2): 535-543 (2010)
Conference and Workshop Papers
- 2005
- [c10]Annie Avakian, Iyad Ouaiss:
Optimizing register binding in FPGAs using simulated annealing. ReConFig 2005 - 2004
- [c9]Hassan Al Atat, Iyad Ouaiss:
Register Binding for FPGAs with Embedded Memory. FCCM 2004: 167-175 - [c8]Dalia Dagher, Iyad Ouaiss:
Storage Allocation for Diverse FPGA Memory Specifications. FPL 2004: 606-616 - 2001
- [c7]Iyad Ouaiss, Ranga Vemuri:
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. DATE 2001: 650-657 - [c6]Amit Kasat, Iyad Ouaiss, Ranga Vemuri:
Memory Synthesis for FPGA-Based Reconfigurable Computers. FPL 2001: 70-80 - [c5]Iyad Ouaiss, Ranga Vemuri:
Global memory mapping for FPGA-based reconfigurable systems. IPDPS 2001: 144 - 2000
- [c4]Iyad Ouaiss, Ranga Vemuri:
Efficient Resource Arbitration in Reconfigurable Computing Environments. DATE 2000: 560-566 - 1999
- [c3]Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss:
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. DAC 1999: 616-622 - 1998
- [c2]Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri:
An Effective Design System for Dynamically Reconfigurable Architectures. FCCM 1998: 312-313 - [c1]Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri:
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops 1998: 31-36
Coauthor Index
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