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Giovanni Battista Gerace
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1970 – 1979
- 1976
- [j10]Graziano Frosini, Giovanni B. Gerace:
Synchronous and Asynchronous Procedures for the Synthesis of Master-Slave Circuits. IEEE Trans. Computers 25(11): 1179-1184 (1976) - 1971
- [j9]Graziano Frosini, Giovanni B. Gerace:
Pulse Input Asynchronous Sequential Circuits. IEEE Trans. Computers 20(4): 436-442 (1971) - [j8]Giovanni Battista Gerace, Luigi Gilli, Piero Maestrini, Angelo Raffaele Meo:
TOPI - A Special-Purpose Computer for Boolean Analysis and Synthesis. IEEE Trans. Computers 20(8): 837-842 (1971) - [j7]Graziano Frosini, Giovanni B. Gerace:
A Universal STT State Assignment Method for Pulse Input Asynchronous Sequential Circuits. IEEE Trans. Computers 20(8): 856-861 (1971) - [c1]Graziano Frosini, Giovanni B. Gerace:
Synthesis of Asynchronous Sequential Circuits with Master-Slave Subcircuits. SWAT 1971: 60-78
1960 – 1969
- 1969
- [j6]Giovanni B. Gerace, Giuseppe Gestri:
Sequential Machines with Less Delay Elements than Feedback Paths. IEEE Trans. Computers 18(2): 132-144 (1969) - 1968
- [j5]Giovanni B. Gerace, G. Gestri:
Decomposition of a Synchronous Machine into an Asynchronous Submachine driving a Synchronous One. Inf. Control. 12(5/6): 538-548 (1968) - [j4]Giovanni B. Gerace:
Digital System Design Automation - A Method for Designing a Digital System as a Sequential Network System. IEEE Trans. Computers 17(11): 1044-1061 (1968) - 1967
- [j3]Giovanni B. Gerace, G. Gestri:
State Assignments for Reducing the Number of Delay Elements in Sequential Machines. Inf. Control. 10(3): 223-253 (1967) - [j2]Giovanni B. Gerace, G. Gestri:
Decomposition of Synchronous Sequential Machines into Synchronous and Asynchronous Submachines. Inf. Control. 11(5/6): 568-591 (1967) - 1963
- [j1]Giovanni Battista Gerace:
Microprogrammed Control for Computing Systems. IEEE Trans. Electron. Comput. 12(6): 733-747 (1963)
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