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Jianliang Ma
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2020 – today
- 2024
- [c17]Weipeng Yang, Hongxia Gao, Wenbin Zou, Tongtong Liu, Shasha Huang, Jianliang Ma:
Low-Light Image Enhancement via Weighted Low-Rank Tensor Regularized Retinex Model. ICMR 2024: 767-775 - 2023
- [j3]Weipeng Yang, Hongxia Gao, Wenbin Zou, Shasha Huang, Hongsheng Chen, Jianliang Ma:
Enhancing Low-Light Images: A Variation-based Retinex with Modified Bilateral Total Variation and Tensor Sparse Coding. Comput. Graph. Forum 42(7) (2023) - [c16]Shasha Huang, Wenbin Zou, Hongxia Gao, Weipeng Yang, Hongsheng Chen, Shicheng Niu, Tian Qi, Jianliang Ma:
Joint Edge-Guided and Spectral Transformation Network for Self-supervised X-Ray Image Restoration. ICANN (2) 2023: 409-420 - [c15]Hongsheng Chen, Wenbin Zou, Hongxia Gao, Weipeng Yang, Shasha Huang, Jianliang Ma:
Joint Priors-Based Restoration Method for Degraded Images Under Medium Propagation. PRCV (11) 2023: 339-350
2010 – 2019
- 2015
- [j2]Jianliang Ma, Licheng Yu, John M. Ye, Tianzhou Chen:
MCMG simulator: A unified simulation framework for CPU and graphic GPU. J. Comput. Syst. Sci. 81(1): 57-71 (2015) - [c14]Jianliang Ma, Tianzhou Chen, Minghui Wu:
Making GPU Warp Scheduler and Memory Scheduler Synchronization-Aware. CloudCom-Asia 2015: 153-164 - [c13]Songyuan Li, Jinglei Meng, Licheng Yu, Jianliang Ma, Tianzhou Chen, Minghui Wu:
Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System. HPCC/CSS/ICESS 2015: 266-271 - [c12]Jianliang Ma, Licheng Yu, Tianzhou Chen, Minghui Wu:
Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture. ISPDC 2015: 90-99 - 2014
- [c11]Jianliang Ma, Jinglei Meng, Tianzhou Chen, Qingsong Shi, Minghui Wu, Li Liu:
Improve LLC Bypassing Performance by Memory Controller Improvements in Heterogeneous Multicore System. PDCAT 2014: 82-89 - 2013
- [c10]Tianzhou Chen, Jinglei Meng, Jianliang Ma, Baixing Quan, Jianzhong Wu:
Phase Based and Application Based Dynamic Encoding Scheme for Multi-level Cell STT-RAM. HPCC/EUC 2013: 1-8 - [c9]Jun Yao, Jianliang Ma, Tianzhou Chen, Tongsen Hu:
An Energy-Efficient Scheme for STT-RAM L1 Cache. HPCC/EUC 2013: 1345-1350 - 2012
- [j1]Jianliang Ma, Chunhao Wang, Baozhong Yu, Tianzhou Chen:
Global register alias table: Boosting sequential program on multi-core. Future Gener. Comput. Syst. 28(6): 957-964 (2012) - [c8]Jianliang Ma, Shaobin Zhang, Tongsen Hu, Minghui Wu, Tianzhou Chen:
Parallel Speculative Dom-based XML Parser. HPCC-ICESS 2012: 33-40 - [c7]Tianzhou Chen, Xingsheng Tang, Licheng Yu, Jianliang Ma, Minghui Wu:
Improve GPGPU Latency Hiding with a Hybrid Recovery Stack and a Window Based Warp Scheduling Policy. HPCC-ICESS 2012: 1288-1293 - 2011
- [c6]Baozhong Yu, Jianliang Ma, Tianzhou Chen, Minghui Wu:
Global Priority Table for Last-Level Caches. DASC 2011: 279-285 - [c5]Baozhong Yu, Yifan Hu, Jianliang Ma, Tianzhou Chen:
Access Pattern Based Re-reference Interval Table for Last Level Cache. PDCAT 2011: 251-256 - 2010
- [c4]Wei Hu, Jianliang Ma, Binbin Wu, Lihan Ju, Tianzhou Chen:
Distributed On-Chip Operating System for Network on Chip. CIT 2010: 2760-2767 - [c3]Tianzhou Chen, Xingsheng Tang, Jianliang Ma, Lihan Ju, Guanjun Jiang, Qingsong Shi:
Single Thread Program Parallelism with Dataflow Abstracting Thread. ICA3PP (2) 2010: 11-21 - [c2]Tianzhou Chen, Jianliang Ma, Hui Yuan, Jingwei Liu, Guanjun Jiang:
Function Units Sharing between Neighbor Cores in CMP. ICA3PP (1) 2010: 136-148
2000 – 2009
- 2009
- [c1]Gang Wang, Du Chen, Jian Chen, Jianliang Ma, Tianzhou Chen:
A Performance Model for Run-Time Reconfigurable Hardware Accelerator. APPT 2009: 54-66
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