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ORCIDAlvin Leng Sun Loke
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2020 – today
- 2023
[c10]Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi, Gaurav Agrawal, Krishna Thakur, Deependra Kumar Jain, Alvin Leng Sun Loke, Atul Kumar, Manish Kumar Upadhyay, Bhawna, Sanjoy Kumar Dey:
Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits. VLSID 2023: 98-103- 2020
- [c9]Wei-Chih Chen, Chin-Hua Wen, Chin-Ming Fu, Tsung-Hsien Tsai, Yu-Chi Chen, Wen-Hung Huang, Chien-Chun Tsai, Alvin Leng Sun Loke, C. H. Kenny:
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. VLSI Circuits 2020: 1-2 - [c8]Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen:
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c7]Alvin Leng Sun Loke, C. K. Lee, Burton Mike Leary:
Nanoscale CMOS Implications on Analog/Mixed-Signal Design. CICC 2019: 1-57 - [c6]Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary:
Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. CICC 2019: 1-8 - 2018
- [c5]Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary:
Analog/mixed-signal design challenges in 7-nm CMOS and beyond. CICC 2018: 1-8 - 2012
- [j4]Hasnain Lakdawala, Alvin Leng Sun Loke:
Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 47(8): 1798-1799 (2012) - [j3]Alvin Leng Sun Loke, Bruce Andrew Doyle, Sanjeev K. Maheshwari, Dennis Michael Fischette, Charles Lin Wang, Tin Tin Wee, Emerson S. Fang:
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. IEEE J. Solid State Circuits 47(11): 2627-2642 (2012) - 2011
- [c4]Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang:
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. A-SSCC 2011: 133-136 - 2010
- [j2]Dennis Michael Fischette, Alvin Leng Sun Loke, Richard Joseph DeSantis, Gerry R. Talbot:
An Embedded All-Digital Circuit to Measure PLL Response. IEEE J. Solid State Circuits 45(8): 1492-1503 (2010) - [c3]Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang:
A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. ISSCC 2010: 246-247
2000 – 2009
- 2009
- [c2]Alvin Leng Sun Loke, Bruce Andrew Doyle, Michael M. Oshima, Wade L. Williams, Robert G. Lewis, Charles Lin Wang, Audie Hanpachern, Karen M. Tucker, Prashanth Gurunath, Gladney C. Asada, Chad O. Lackey, Tin Tin Wee, Emerson S. Fang:
Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links. CICC 2009: 605-608 - 2006
- [j1]Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Michael J. Gilsdorf:
A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. IEEE J. Solid State Circuits 41(8): 1894-1907 (2006) - 2005
- [c1]Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf:
A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking. CICC 2005: 553-556
Coauthor Index
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