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2020 – today
- 2024
[j6]Wanyuan Pan
, Yihe Yu, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu:
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3538-3542 (2024)- 2023
- [j5]Xing Jin, Ningyuan Yin, Weichong Chen, Ximing Li, Guihua Zhao, Zhiyi Yu:
A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations. IEICE Electron. Express 20(11): 20230152 (2023) - [j4]Ximing Li, Xing Jin, Weichong Chen, Ningyuan Yin, Zhiyi Yu:
Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 761-765 (2023) - [j3]Xing Jin, Weichong Chen, Ximing Li, Ningyuan Yin, Caihua Wan, Mingkun Zhao, Xiufeng Han, Zhiyi Yu:
High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 781-785 (2023) - 2022
- [j2]Guihua Zhao, Xing Jin, Huafeng Ye, Yating Peng, Wei Liu, Ningyuan Yin, Weichong Chen, Jianjun Chen, Ximing Li, Zhiyi Yu:
An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks. IEICE Electron. Express 19(20): 20220399 (2022) - 2021
- [j1]Ningyuan Yin, Baofa Huang, Xiaobai Chen, Jianjun Chen, Zhiyi Yu:
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 311-321 (2021)
2010 – 2019
- 2017
- [c2]Baofa Huang, Ningyuan Yin, Zhiyi Yu:
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. ASICON 2017: 383-386 - 2013
- [c1]Ningyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu:
A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC. ASICON 2013: 1-4
Coauthor Index
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