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Lukasz G. Szafaryn

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2010 – 2019

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2019
[c5]
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  - conf/hpca/GanapathyKBRS19
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Shrikanth Ganapathy, John Kalamatianos, Bradford M. Beckmann, Steven Raasch, Lukasz G. Szafaryn:
Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST. HPCA 2019: 304-316
2018
[j3]
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  - journals/tcad/ChengMSCCSSLABM18
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Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1839-1852 (2018)
2017
[c4]
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  - conf/iccd/ChengABBCCCCLLM17
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Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596
[i2]
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  - journals/corr/abs-1709-09921
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Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). CoRR abs/1709.09921 (2017)
2016
[c3]
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Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. DAC 2016: 68:1-68:6
[i1]
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Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores. CoRR abs/1604.03062 (2016)
2014
[c2]
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  - conf/vlsi-dat/MitraBCCCJKLLRS14
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Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn:
The resilience wall: Cross-layer solution strategies. VLSI-DAT 2014: 1-11
2013
[j2]
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  - journals/jpdc/SzafarynGSS13
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Lukasz G. Szafaryn, Todd Gamblin, Bronis R. de Supinski, Kevin Skadron:
Trellis: Portability across architectures with a high-level framework. J. Parallel Distributed Comput. 73(10): 1400-1413 (2013)
[j1]
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Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron:
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core. IEEE Micro 33(4): 56-65 (2013)
2010
[c1]
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  - conf/iiswc/CheSBSWS10
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Shuai Che, Jeremy W. Sheaffer, Michael Boyer, Lukasz G. Szafaryn, Liang Wang, Kevin Skadron:
A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads. IISWC 2010: 1-11

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