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ORCIDAritra Dasgupta 0002
Person information
- affiliation: University of Florida, Gainesville, FL, USA
Other persons with the same name
- Aritra Dasgupta 0001
![[0000-0002-5551-5103]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-5551-5103")
— New Jersey Institute of Technology, Newark, USA - Aritra Dasgupta 0003 — ZURU Tech India Pvt. Ltd, Kolkata, India (and 1 more)
- Aritra Dasgupta 0004 — Pacific Northwest National Laboratory, USA
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2020 – today
- 2025
[c11]Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia:
CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking. VTS 2025: 1-7- [c10]Sudipta Paria, Aritra Dasgupta, Swarup Bhunia:
Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages. VTS 2025: 1-5 - [i5]Aritra Dasgupta, Sudipta Paria, Christopher Sozio, Andrew Lukefahr, Swarup Bhunia:
Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection. CoRR abs/2501.12292 (2025) - [i4]Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Venkat Nitin Patnala, Swarup Bhunia, Sai Manoj PD:
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs. CoRR abs/2504.18812 (2025) - [i3]Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia:
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation. CoRR abs/2505.19418 (2025) - [i2]Aritra Dasgupta, Sudipta Paria, Swarup Bhunia:
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction. IACR Cryptol. ePrint Arch. 2025: 553 (2025) - 2024
- [j2]Sudipta Paria, Aritra Dasgupta, Swarup Bhunia:
SPELL: An End-to-End Tool Flow for LLM-Guided Secure SoC Design for Embedded Systems. IEEE Embed. Syst. Lett. 16(4): 365-368 (2024) - [j1]Shubhra Deb Paul, Aritra Dasgupta, Swarup Bhunia:
FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 3479-3490 (2024) - [c9]Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia:
LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection. ATS 2024: 1-6 - [c8]Sudipta Paria, Aritra Dasgupta, Swarup Bhunia:
Navigating SoC Security Landscape on LLM-Guided Paths. ACM Great Lakes Symposium on VLSI 2024: 252-257 - [c7]Rasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, Swarup Bhunia:
LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations. ACM Great Lakes Symposium on VLSI 2024: 588-591 - [c6]Sudipta Paria, Aritra Dasgupta, Swarup Bhunia:
DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement. HOST 2024: 271-281 - [c5]Aritra Dasgupta, Sudipta Paria, Prabuddha Chakraborty, Swarup Bhunia:
Splitting the Secrets: A Cooperative Trust Model for System-on-Chip Designs with Untrusted IPs. ISVLSI 2024: 325-330 - [c4]Rasheed Almawzan, Sudipta Paria, Aritra Dasgupta, Kostas Amberiadis, Swarup Bhunia:
IP Security in Structured ASIC: Challenges and Prospects. ISVLSI 2024: 397-402 - [c3]Reiner N. Dizon-Paradis, Aritra Dasgupta, Rohan Reddy Kalavakonda, Swarup Bhunia:
Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications. ISVLSI 2024: 539-543 - 2023
- [c2]Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet:
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware. VTS 2023: 1-7 - [i1]Sudipta Paria, Aritra Dasgupta, Swarup Bhunia:
DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection. CoRR abs/2308.06932 (2023) - 2022
- [c1]Abdulrahman Alaql, Aritra Dasgupta, Md. Moshiur Rahman, Swarup Bhunia:
SEVA: Structural Analysis based Security Evaluation of Sequential Locking. VLSID 2022: 126-131
Coauthor Index
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