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ORCIDShan Huang 0010
Person information
- affiliation: Shanghai Jiao Tong University, Shanghai, China
Other persons with the same name
- Shan Huang — disambiguation page
- Shan Huang 0001 — Boston University, Department of Physics, MA, USA
- Shan Huang 0002
![[0000-0002-6140-0206]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-6140-0206")
— National University of Defense Technology, NUDT, College of Computer Science, China - Shan Huang 0003 — Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
- Shan Huang 0004 — Xi'an Jiaotong University, School of Information and Communications Engineering, China
- Shan Huang 0005 — Wuhan University, School of Electronic Information, Signal Processing Laboratory, China
- Shan Huang 0006 — University of California, Los Angeles, UCLA, CA, USA
- Shan Huang 0007 — Northeastern University, School of Computer Science and Engineering, Shenyang, China
- Shan Huang 0008 — University of Illinois Urbana-Champaign, Urbana, IL, USA
- Shan Huang 0009 — Jinan University, Guangzhou, China
- Shan Huang 0011 — Beijing University of Posts and Telecommunications, Beijing, China
- Shan Huang 0012 — University of Hong Kong, Hong Kong, Hong Kong, SAR, China
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2020 – today
- 2025
[j1]Jiaming Xu, Shan Huang, Jinhao Li, Guyue Huang, Yuan Xie, Yu Wang, Guohao Dai:
Enabling Efficient Sparse Multiplications on GPUs With Heuristic Adaptability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(6): 2226-2239 (2025)- [c7]Li Ding, Jun Liu, Shan Huang, Guohao Dai:
ViDA: Video Diffusion Transformer Acceleration with Differential Approximation and Adaptive Dataflow. ASP-DAC 2025: 148-154 - [c6]Shan Huang, Jinhao Li, Zhen Yu, Jiancai Ye, Jiaming Xu, Ningyi Xu, Guohao Dai:
LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration. ASP-DAC 2025: 974-980 - [c5]Changran Xu, Yi Liu, Yunhao Zhou, Shan Huang, Ningyi Xu, Qiang Xu:
Speculative Decoding for Verilog: Speed and Quality, All in One. DAC 2025: 1-7 - [c4]Zhen Yu, Jinhao Li, Jiaming Xu, Shan Huang, Jiancai Ye, Ningyi Xu, Guohao Dai:
DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Partitioning, Low-Degree Sparsity, and Asynchronous Sub-Batch. DATE 2025: 1-7 - [c3]Ziyang Zheng, Shan Huang, Jianyuan Zhong, Zhengyuan Shi, Guohao Dai, Ningyi Xu, Qiang Xu:
DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale. ICLR 2025 - [i5]Ziyang Zheng, Shan Huang, Jianyuan Zhong, Zhengyuan Shi, Guohao Dai, Ningyi Xu, Qiang Xu:
DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale. CoRR abs/2502.01681 (2025) - [i4]Changran Xu, Yi Liu, Yunhao Zhou, Shan Huang, Ningyi Xu, Qiang Xu:
Speculative Decoding for Verilog: Speed and Quality, All in One. CoRR abs/2503.14153 (2025) - 2024
- [c2]Jinhao Li, Jiaming Xu, Shiyao Li, Shan Huang, Jun Liu, Yaoxiu Lian, Guohao Dai:
Fast and Efficient 2-bit LLM Inference on GPU: 2/4/16-bit in a Weight Matrix with Asynchronous Dequantization. ICCAD 2024: 150:1-150:9 - [c1]Jinhao Li, Shan Huang, Jiaming Xu, Jun Liu, Li Ding, Ningyi Xu, Guohao Dai:
MARCA: Mamba Accelerator with Reconfigurable Architecture. ICCAD 2024: 234:1-234:9 - [i3]Jinhao Li, Shan Huang, Jiaming Xu, Jun Liu, Li Ding, Ningyi Xu, Guohao Dai:
MARCA: Mamba Accelerator with ReConfigurable Architecture. CoRR abs/2409.11440 (2024) - [i2]Jinhao Li, Jiaming Xu, Shan Huang, Yonghua Chen, Wen Li, Jun Liu, Yaoxiu Lian, Jiayi Pan, Li Ding, Hao Zhou, Yu Wang, Guohao Dai:
Large Language Model Inference Acceleration: A Comprehensive Hardware Perspective. CoRR abs/2410.04466 (2024) - 2023
- [i1]Jinhao Li, Jiaming Xu, Shiyao Li, Shan Huang, Jun Liu, Yaoxiu Lian, Guohao Dai:
Fast and Efficient 2-bit LLM Inference on GPU: 2/4/16-bit in a Weight Matrix with Asynchronous Dequantization. CoRR abs/2311.16442 (2023)
Coauthor Index
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