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Journal Articles
- 2018
[j4]Eduardo Viegas
, Altair Olivo Santin, Luiz Oliveira, André França, Ricardo P. Jasinski, Volnei A. Pedroni:
A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems. Comput. Secur. 78: 16-32 (2018)- 2017
- [j3]Eduardo Viegas, Altair Olivo Santin, André França, Ricardo P. Jasinski, Volnei A. Pedroni, Luiz S. Oliveira:
Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded Systems. IEEE Trans. Computers 66(1): 163-177 (2017) - 2010
- [j2]Ricardo P. Jasinski:
Jari Nurmi: Processor Design - System-on-Chip Computing for ASICs and FPGAs. Springer (2007) ISBN 978-1-4020-5529-4. Comput. J. 53(1): 127 (2010) - 2007
- [j1]Ricardo P. Jasinski:
Fault-Tolerance Techniques for SRAM-Based FPGAs. Comput. J. 50(2): 248 (2007)
Conference and Workshop Papers
- 2016
- [c10]Marcelo de Oliveira Rosa, Caio Cesar Viana da Silva, Wyllian Bezerra da Silva, Ricardo P. Jasinski, Volnei Antonio Pedroni, Alexandre de Almeida Prado Pohl:
Extraction of spatio-temporal features based on a hardware approach for a no-reference objective video quality metric. BMSB 2016: 1-4 - 2015
- [c9]André Luiz Pereira de França, Ricardo P. Jasinski, Paulo Cemin, Volnei A. Pedroni, Altair Olivo Santin:
The energy cost of network security: A hardware vs. software comparison. ISCAS 2015: 81-84 - 2014
- [c8]André Luiz Pereira de França, Ricardo Pereira Jasinski, Volnei Antonio Pedroni, Altair Olivo Santin:
Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis. ISVLSI 2014: 456-461 - 2012
- [c7]Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean M. Simao:
A new hardware coprocessor for accelerating Notification-Oriented applications. FPT 2012: 257-260 - 2011
- [c6]Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni:
A very efficient single-iteration oldest-out data sorter. ISCAS 2011: 2141-2144 - 2010
- [c5]Antonio Gortan, Ricardo P. Jasinski, Walter Godoy Jr., Volnei A. Pedroni:
Achieving near-MLD performance with soft information-set decoders implemented in FPGAs. APCCAS 2010: 312-315 - [c4]Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni:
Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors. APCCAS 2010: 923-926 - [c3]Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni:
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart. ReConFig 2010: 127-131 - [c2]Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.:
An Improved GF(2) Matrix Inverter with Linear Time Complexity. ReConFig 2010: 322-327 - 2004
- [c1]Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni:
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs. ISCAS (1) 2004: 1088-1091
Coauthor Index
aka: Volnei Antonio Pedroni
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