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2020 – today
- 2024
[c13]Runyu Jin
, Paul Muench, Travis Janssen, Brian Hatfield, Veera Deenadhayalan:
Baking Disaster-Proof Kubernetes Applications with Efficient Recipes. ICPE (Companion) 2024: 174-180- [i1]Talia Gershon, Seetharami Seelam, Brian Belgodere, Milton Bonilla, Lan Hoang, Danny Barnett, I-Hsin Chung, Apoorve Mohan, Ming-Hung Chen, Lixiang Luo, Robert Walkup, Constantinos Evangelinos, Shweta Salaria, Marc Dombrowa, Yoonho Park, Apo Kayi, Liran Schour, Alim Alim, Ali Sydney, Pavlos Maniotis, Laurent Schares, Bernard Metzler, Bengi Karacali-Akyamac, Sophia Wen, Tatsuhiro Chiba, Sunyanan Choochotkaew, Takeshi Yoshimura, Claudia Misale, Tonia Elengikal, Kevin O. Connor, Zhuoran Liu, Richard Molina, Lars Schneidenbach, James Caden, Christopher Laibinis, Carlos Fonseca, Vasily Tarasov, Swaminathan Sundararaman, Frank B. Schmuck, Scott Guthridge, Jeremy Cohn, Marc Eshel, Paul Muench, Runyu Liu, William Pointer, Drew Wyskida, Bob Krull, Ray Rose, Brent Wolfe, William Cornejo, John Walter, Colm Malone, Clifford Perucci, Frank Franco, Nigel Hinds, Bob Calio, Pavel Druyan, Robert Kilduff, John Kienle, Connor McStay, Andrew Figueroa, Matthew Connolly, Edie Fost, Gina Roma, Jake Fonseca, Ido Levy, Michele Payne, Ryan Schenkel, Amir Malki, Lion Schneider, Aniruddha Narkhede, Shekeba Moshref, Alexandra Kisin, Olga Dodin, Bill Rippon, Henry Wrieth, John Ganci, Johnny Colino, Donna Habeger-Rose, Rakesh Pandey, Aditya Gidh, Aditya Gaur, Dennis Patterson, Samsuddin Salmani, Rambilas Varma, Rumana Rumana, Shubham Sharma, Mayank Mishra, Rameswar Panda, Aditya Prasad, Matt Stallone, Gaoyuan Zhang, Yikang Shen, David Cox, Ruchir Puri, Dakshi Agrawal, Drew Thorstensen, Joel Belog, Brent Tang:
The infrastructure powering IBM's Gen AI model development. CoRR abs/2407.05467 (2024) - 2022
- [c12]Runyu Jin, Paul Muench, Veera Deenadhayalan, Brian Hatfield:
AIOps Essential to Unified Resiliency Management in Data Lakehouses. IEEE Big Data 2022: 4777-4781 - 2021
- [c11]Mario Blaum, Paul Muench:
Reliability of Centralized vs. Parallel Software Models for Composable Storage Systems. QRS 2021: 534-542
2010 – 2019
- 2018
- [j3]Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench:
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53(1): 91-101 (2018) - 2017
- [c10]Sangeetha Seshadri, Paul Muench, Lawrence Chiu:
Trillion Operations Key-Value Storage Engine: Revisiting the Mission Critical Analytics Storage Software Stack. ICDCS 2017: 1865-1872 - [c9]Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis:
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ISSCC 2017: 444-445 - 2015
- [j2]Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - 2014
- [j1]Sangeetha Seshadri, Paul Muench, Lawrence Chiu, Ioannis Koltsidas, Nikolas Ioannou, Robert Haas, Yang Liu, Mei Mei, Stephen Blinick:
Software defined just-in-time caching in an enterprise storage system. IBM J. Res. Dev. 58(2/3) (2014) - [c8]Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. ISSCC 2014: 98-99 - [c7]Hyojun Kim, Ioannis Koltsidas, Nikolas Ioannou, Sangeetha Seshadri, Paul Muench, Clement L. Dickey, Lawrence Chiu:
How Could a Flash Cache Degrade Database Performance Rather Than Improve It? Lessons to be Learnt from Multi-Tiered Storage. INFLOW 2014 - [c6]Hyojun Kim, Ioannis Koltsidas, Nikolas Ioannou, Sangeetha Seshadri, Paul Muench, Clement L. Dickey, Lawrence Chiu:
Flash-Conscious Cache Population for Enterprise Database Workloads. ADMS@VLDB 2014: 45-56 - 2010
- [c5]Gong Zhang, Lawrence Chiu, Clem Dickey, Ling Liu, Paul Muench, Sangeetha Seshadri:
Automated lookahead data migration in SSD-enabled multi-tiered storage systems. MSST 2010: 1-6
2000 – 2009
- 2008
- [c4]Sangeetha Seshadri, Lawrence Chiu, Cornel Constantinescu, Subashini Balachandran, Clem Dickey, Ling Liu, Paul Muench:
Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling. FAST 2008: 143-158 - [c3]Peilin Song, Stephen Ippolito, Franco Stellari, John Sylvestri, Tim Diemoz, George Smith, Paul Muench, Norm James, Seongwon Kim, Hector Saenz:
Optical Diagnostics for IBM POWER6- Microprocessor. ITC 2008: 1-9 - 2007
- [c2]Sangeetha Seshadri, Ling Liu, Brian F. Cooper, Lawrence Chiu, Karan Gupta, Paul Muench:
A Fault-Tolerant Middleware Architecture for High-Availability Storage Services. IEEE SCC 2007: 286-293 - 2004
- [c1]Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson:
Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672
Coauthor Index
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