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2020 – today
- 2022
[j16]Francesc Salvat
, Josep Llosa, Antonio M. Lallena, Julio Almansa:
ECCPA: Calculation of classical and quantum cross sections for elastic collisions of charged particles with atoms. Comput. Phys. Commun. 277: 108368 (2022)- [c35]Apan Qasem, Hartwig Anzt, Eduard Ayguadé, Katharine J. Cahill, Ramon Canal, Jany Chan, Eric Fosler-Lussier, Fritz Göbel, Arpan Jain, Marcel Koch, Mateusz Kuzak, Josep Llosa, Raghu Machiraju, Xavier Martorell, Pratik Nayak, Shameema Oottikkal, Marcin Ostasz, Dhabaleswar K. Panda, Dirk Pleiter, Rajiv Ramnath, Maria-Ribera Sancho, Alessio Sclocco, Aamir Shafi, Hanno Spreeuw, Hari Subramoni, Karen Tomko:
Lightning Talks of EduHPC 2022. EduHPC@SC 2022: 42-49
2010 – 2019
- 2010
- [j15]Manoj Gupta, Fermín Sánchez, Josep Llosa:
CSMT: Simultaneous Multithreading for Clustered VLIW Processors. IEEE Trans. Computers 59(3): 385-399 (2010) - [c34]Manoj Gupta, Fermín Sánchez, Josep Llosa:
A low cost split-issue technique to improve performance of SMT clustered VLIW processors. IPDPS 2010: 1-12
2000 – 2009
- 2009
- [c33]Manoj Gupta, Fermín Sánchez, Josep Llosa:
Hybrid multithreading for VLIW processors. CASES 2009: 37-46 - [c32]Manoj Gupta, Fermín Sánchez, Josep Llosa:
Thread Merging Schemes for Multithreaded Clustered VLIW Processors. ICPP 2009: 445-452 - 2008
- [j14]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Power-efficient VLIW design using clustering and widening. Int. J. Embed. Syst. 3(3): 141-149 (2008) - 2007
- [c31]Kolin Paul, Joël Porquet, Josep Llosa:
Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. DSD 2007: 317-324 - [c30]Manoj Gupta, Fermín Sánchez, Josep Llosa:
Merge Logic for Clustered Multithreaded VLIW Processors. DSD 2007: 353-360 - [c29]Manoj Gupta, Fermín Sánchez, Josep Llosa:
Cluster-level simultaneous multithreading for VLIW processors. ICCD 2007: 121-128 - 2005
- [j13]Xavier Vera, Jaume Abella, Josep Llosa, Antonio González:
An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. 27(5): 946-987 (2005) - 2004
- [j12]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
High-performance and low-power VLIW cores for numerical computations. Int. J. High Perform. Comput. Netw. 1(4): 171-179 (2004) - [j11]Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega:
Future ILP processors. Int. J. High Perform. Comput. Netw. 2(1): 1-10 (2004) - [j10]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. Int. J. Parallel Program. 32(6): 447-474 (2004) - [j9]Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero:
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. SIGARCH Comput. Archit. News 32(3): 3-10 (2004) - [j8]Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González:
A fast and accurate framework to analyze and optimize cache memory behavior. ACM Trans. Program. Lang. Syst. 26(2): 263-300 (2004) - [j7]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Register Constrained Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 15(5): 417-430 (2004) - [c28]Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero:
Out-of-Order Commit Processors. HPCA 2004: 48-59 - [c27]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. SAMOS 2004: 88-97 - 2003
- [j6]Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero:
A Case for Resource-conscious Out-of-order Processors. IEEE Comput. Archit. Lett. 2 (2003) - [c26]Xavier Vera, Jaume Abella, Antonio González, Josep Llosa:
Optimizing Program Locality Through CMEs and GAs. IEEE PACT 2003: 68-78 - [c25]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Hierarchical Clustered Register File Organization for VLIW Processors. IPDPS 2003: 77 - [c24]Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero:
Kilo-instruction Processors. ISHPC 2003: 10-25 - [c23]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ISHPC 2003: 113-126 - 2002
- [c22]Jaume Abella, Antonio González, Josep Llosa, Xavier Vera:
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops 2002: 568-580 - [c21]Josep M. Codina, Josep Llosa, Antonio González:
A comparative study of modulo scheduling techniques. ICS 2002: 97-106 - [c20]Xavier Vera, Josep Llosa, Antonio González:
Near-Optimal Padding for Removing Conflict Misses. LCPC 2002: 329-343 - [c19]Josep Llosa, Stefan M. Freudenberger:
Reduced code size modulo scheduling in the absence of hardware support. MICRO 2002: 99-110 - 2001
- [j5]Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt:
Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers 50(3): 234-249 (2001) - [j4]David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Trans. Computers 50(10): 1033-1051 (2001) - [c18]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
MIRS: Modulo Scheduling with Integrated Register Spilling. LCPC 2001: 239-253 - [c17]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Modulo scheduling with integrated register spilling for clustered VLIW architectures. MICRO 2001: 160-169 - 2000
- [j3]Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa:
Optimizing cache miss equations polyhedra. SIGARCH Comput. Archit. News 28(1): 43-52 (2000) - [c16]Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo:
A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). Euro-Par 2000: 194-198 - [c15]Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa:
An efficient solver for Cache Miss Equations. ISPASS 2000: 139-145 - [c14]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Two-level hierarchical register file organization for VLIW processors. MICRO 2000: 137-146 - [c13]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Improved spill code generation for software pipelined loops. PLDI 2000: 134-144
1990 – 1999
- 1999
- [c12]Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham:
Distributed Modulo Scheduling. HPCA 1999: 130-134 - [c11]David López, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ICPP 1999: 22-29 - 1998
- [j2]Josep Llosa, Eduard Ayguadé, Mateo Valero:
Quantitative Evaluation of Register Pressure on Software Pipelined Loops. Int. J. Parallel Program. 26(2): 121-142 (1998) - [j1]Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers 47(6): 625-638 (1998) - [c10]David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Resource Widening Versus Replication: Limits and Performance-cost Trade-off. International Conference on Supercomputing 1998: 441-448 - [c9]Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham:
Partitioned Schedules for Clustered VLIW Architectures. IPPS/SPDP 1998: 386-391 - [c8]David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. MICRO 1998: 237-246 - 1997
- [c7]Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham:
Allocating Lifetimes to Queues in Software Pipelined Architectures. Euro-Par 1997: 1066-1073 - [c6]David López, Mateo Valero, Josep Llosa, Eduard Ayguadé:
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. International Conference on Supercomputing 1997: 12-19 - 1996
- [c5]Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero:
Swing module scheduling: a lifetime-sensitive approach. IEEE PACT 1996: 80-86 - [c4]Josep Llosa, Mateo Valero, Eduard Ayguadé:
Heuristics for Register-Constrained Software Pipelining. MICRO 1996: 250-261 - 1995
- [c3]Josep Llosa, Mateo Valero, Eduard Ayguadé:
Non-Consistent Dual Register Files to Reduce Register Pressure. HPCA 1995: 22-31 - [c2]Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Hypernode reduction modulo scheduling. MICRO 1995: 350-360 - 1994
- [c1]Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé:
Using Sacks to Organize Registers in VLIW Machines. CONPAR 1994: 628-639
Coauthor Index
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