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2020 – today
- 2023
[j5]Ho-Jin Kim
, Jun-Ho Boo, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn:
A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 401-405 (2023)- 2021
- [j4]Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn:
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. IEEE J. Solid State Circuits 56(4): 1197-1206 (2021) - [c10]Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho Ahn:
A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. A-SSCC 2021: 1-3 - 2020
- [c9]Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Jun-Sang Park, Seung-Hoon Lee, Gil-Cho Ahn:
A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. A-SSCC 2020: 1-2 - [c8]Tae-Gwan Kim, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn:
A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique. ISOCC 2020: 3-4 - [c7]Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn:
A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, -0.12% for Battery Monitoring Applications. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c6]Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Jun-Ho Boo, Seung-Hoon Lee, Gil-Cho Ahn:
A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. CICC 2019: 1-4 - [c5]Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn:
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. ISOCC 2019: 7-8 - 2018
- [j3]Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Gil-Cho Ahn:
A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture. IEICE Electron. Express 15(21): 20180848 (2018) - [j2]Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn:
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators. IEEE J. Solid State Circuits 53(10): 2772-2782 (2018) - 2017
- [j1]Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn:
A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique. IEICE Electron. Express 14(21): 20171007 (2017) - [c4]Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn:
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators. A-SSCC 2017: 289-292 - 2014
- [c3]Mi-rim Kim, Young-Ouk Kim, Yong-Sik Kwak, Gil-Cho Ahn:
A 12-bit 200-kS/s SAR ADC with hybrid RC DAC. APCCAS 2014: 185-188 - 2012
- [c2]Young-min Park, Tae-In Kwon, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn, Chang-Seob Shin, Myung-Jin Lee, Seung-Bin You, Ho-Jin Park:
A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer. ICECS 2012: 637-640 - [c1]Yong-Sik Kwak, Kwang-Soo Kim, Gil-Cho Ahn:
A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference. ISCAS 2012: 520-523
Coauthor Index
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