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Madhu K. Iyer
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2000 – 2009
- 2005
- [c12]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
:
Structural search for RTL with predicate learning. DAC 2005: 451-456 - [c11]Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
:
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE 2005: 666-671 - [c10]Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang
, Kwang-Ting Cheng
, Kuang-Chien Chen:
An Efficient Sequential SAT Solver With Improved Search Strategies. DATE 2005: 1102-1107 - [c9]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng
, Forrest Brewer
:
RTL SAT simplification by Boolean and interval arithmetic reasoning. ICCAD 2005: 297-302 - 2004
- [j2]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng
, Li-C. Wang
:
Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Des. Test Comput. 21(2): 132-143 (2004) - [c8]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
Efficient reachability checking using sequential SAT. ASP-DAC 2004: 418-423 - [c7]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng
, Li-C. Wang:
An efficient finite-domain constraint solver for circuits. DAC 2004: 212-217 - 2003
- [c6]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng
, Li-C. Wang
:
A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT 2003: 157-162 - [c5]Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng:
SATORI - A Fast Sequential SAT Engine for Circuits. ICCAD 2003: 320-325 - 2002
- [c4]Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC 2002: 203-212 - [c3]Madhu K. Iyer, Kwang-Ting Cheng
:
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. VTS 2002: 139-144 - 2001
- [c2]Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng:
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS 2001: 198-203
1990 – 1999
- 1999
- [j1]Madhu K. Iyer, Michael L. Bushnell:
Effect of Noise on Analog Circuit Testing. J. Electron. Test. 15(1-2): 11-22 (1999) - 1998
- [c1]Madhu K. Iyer, Michael L. Bushnell:
Effect of Noise on Analog Circuit Testing. VTS 1998: 138-144
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