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ORCIDSomnath Paul
- > Home > Persons > Somnath Paul
Publications
- 2017
[j20]Dongyeob Shin, Jongsun Park
, Jangwon Park, Somnath Paul, Swarup Bhunia:
Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Des. Test 34(6): 84-93 (2017)- [j19]Robert Karam, Somnath Paul, Ruchir Puri, Swarup Bhunia:
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications. ACM J. Emerg. Technol. Comput. Syst. 13(3): 34:1-34:24 (2017) - [j17]Wenchao Qian, Christopher Babecki, Robert Karam, Somnath Paul, Swarup Bhunia:
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 177-188 (2017) - 2016
- [j15]Christopher Babecki, Wenchao Qian, Somnath Paul, Robert Karam, Swarup Bhunia:
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications. IEEE Trans. Computers 65(10): 3196-3202 (2016) - 2015
- [j14]Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay:
Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 5-16 (2015) - [j13]Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia:
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1005-1016 (2015) - 2014
- [j10]Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia:
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1314-1327 (2014) - [j9]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia:
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2449-2461 (2014) - [c29]Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri:
Energy-efficient hardware acceleration through computing in the memory. DATE 2014: 1-6 - [c28]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia:
Robust low-power reconfigurable computing with a variation-aware preferential design approach. ICICDT 2014: 1-6 - 2013
- [j7]Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia:
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. IEEE Trans. Computers 62(11): 2183-2195 (2013) - [c27]Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia:
Reconfigurable ECC for adaptive protection of memory. MWSCAS 2013: 1085-1088 - 2012
- [c25]Lei Wang, Somnath Paul, Swarup Bhunia:
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. VLSI Design 2012: 340-345 - [c24]Anandaroop Ghosh, Somnath Paul, Swarup Bhunia:
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. VLSI Design 2012: 424-429 - 2011
- [j5]Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia:
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 369-380 (2011) - [j4]Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia:
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Trans. Computers 60(1): 20-34 (2011) - [j3]Somnath Paul, Swarup Bhunia:
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1368-1379 (2011) - [c23]Somnath Paul, Swarup Bhunia:
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). FPGA 2011: 283 - [c22]Xinmu Wang, Seetharam Narasimhan, Somnath Paul, Swarup Bhunia:
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing. NANOARCH 2011: 210-217 - 2010
- [j2]Somnath Paul, Hamid Mahmoodi, Swarup Bhunia:
Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. ACM Trans. Design Autom. Electr. Syst. 15(2): 19:1-19:34 (2010) - [c21]Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Swarup Bhunia:
System level self-healing for parametric yield and reliability improvement under power bound. AHS 2010: 52-58 - [c20]Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia:
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18 - [c19]Somnath Paul, Swarup Bhunia:
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. ISLPED 2010: 37-42 - 2009
- [j1]Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia:
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. IET Comput. Digit. Tech. 3(6): 609-624 (2009) - [c18]Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia:
MERO: A Statistical Approach for Hardware Trojan Detection. CHES 2009: 396-410 - [c17]Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia:
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. ICCAD 2009: 109-112 - [c16]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia:
A variation-aware preferential design approach for memory based reconfigurable computing. ICCAD 2009: 180-183 - [c15]Somnath Paul, Swarup Bhunia:
Computing with nanoscale memory: Model and architecture. NANOARCH 2009: 1-6 - 2008
- [c14]Somnath Paul, Swarup Bhunia:
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ASP-DAC 2008: 77-82 - [c13]Seetharam Narasimhan, Somnath Paul, Swarup Bhunia:
Collective computing based on swarm intelligence. DAC 2008: 349-350 - [c12]Somnath Paul, Swarup Bhunia:
Reconfigurable computing using content addressable memory for improved performance and resource usage. DAC 2008: 786-791 - [c11]Yu Zhou, Somnath Paul, Swarup Bhunia:
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. DATE 2008: 98-103 - [c10]Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia:
On-Demand Transparency for Improving Hardware Trojan Detectability. HOST 2008: 48-50 - [c9]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia:
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. ICCAD 2008: 589-592 - [c8]Yu Zhou, Somnath Paul, Swarup Bhunia:
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. ISQED 2008: 861-866 - [c7]Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia:
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. VLSI Design 2008: 441-446 - 2007
- [c6]Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia:
Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404 - [c5]Somnath Paul, Swarup Bhunia:
Memory based computation using embedded cache for processor yield and reliability improvement. ICCD 2007: 341-346 - [c4]Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia:
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. IOLTS 2007: 29-36 - [c3]Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia:
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. ISQED 2007: 755-760 - [c2]Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia:
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. VTS 2007: 455-460
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