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ORCIDMarcelo Schiavon Porto
Publications
- 2022
[c126]Pablo Rosa, Daniel Palomino, Marcelo Schiavon Porto, Luciano Agostini:
GM-RF: An AV1 Intra-Frame Fast Decision Based on Random Forest. ICIP 2022: 3556-3560- [c125]Adson Duarte
, Paulo Gonçalves, Luciano Agostini, Bruno Zatt, Guilherme Corrêa, Marcelo Schiavon Porto, Daniel Palomino:
Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination. ISCAS 2022: 1-5 - 2021
- [j18]Marcel Moscarelli Corrêa, Mário Saldanha, Alex Borges, Guilherme Corrêa, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt, Luciano Agostini:
AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design. IEEE Open J. Circuits Syst. 2: 564-576 (2021) - 2020
- [j11]Murilo R. Perleberg, Vinicius Ruela Pereira Borges, Vladimir Afonso, Daniel Palomino, Luciano Agostini, Marcelo Schiavon Porto:
6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 836-840 (2020) - [c114]Alex Borges, Daniel Palomino, Bruno Zatt, Marcelo Schiavon Porto, Guilherme Corrêa:
Fast VP9-to-AV1 Transcoding based on Block Partitioning Inheritance. EUSIPCO 2020: 555-559 - [c113]Ítalo D. Machado, Marilton S. de Aguiar, Marcelo Schiavon Porto, Guilherme Corrêa, Daniel Palomino, Bruno Zatt:
RDE-MOGA: Automatic Selection of Rate-Distortion-Energy Control Points for Video Encoders Using Muti-Objetive Genetic Algorithm. ICASSP 2020: 2208-2212 - [c111]Mário Saldanha, Marcel Moscarelli Corrêa, Guilherme Corrêa, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt, Luciano Agostini:
An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs. ICECS 2020: 1-4 - [c109]Wagner Penny, Guilherme Corrêa, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Gabriel L. Nazar, Bruno Zatt:
Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC. ISCAS 2020: 1-5 - [c108]Eduardo Zummach, Roberta Palau, Jones Goebel, Daniel Palomino, Luciano Agostini, Marcelo Schiavon Porto:
Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD Videos. ISCAS 2020: 1-5 - [c102]Wagner Penny, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt:
Power/QoS-Adaptive HEVC FME Hardware using Machine Learning-Based Approximation Control. VCIP 2020: 78-81 - [c101]Matheus Jahnke, Jones Goebel, Daniel Palomino, Guilherme Corrêa, Luciano Agostini, Marcelo Schiavon Porto, Bruno Zatt:
4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding. VCIP 2020: 132-135 - 2019
- [j8]Robson Domanski, Jones Goebel, Wagner Penny, Marcelo Schiavon Porto, Daniel Palomino, Bruno Zatt, Luciano Agostini:
High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 883-887 (2019) - [c100]Isis Bender, Daniel Palomino, Luciano Agostini, Guilherme Corrêa, Marcelo Schiavon Porto:
Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders. EUSIPCO 2019: 1-5 - [c98]Wagner Penny, Jones Goebel, Douglas Corrêa, Anderson Martins, Gabriel L. Nazar, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt:
Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation. ICECS 2019: 162-165 - [c97]Luciano Almeida Braatz, Antonio Carlos Schneider Beck, Bruno Zatt, Luciano Volcan Agostini, Daniel Munari Palomino, Marcelo Schiavon Porto:
A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design. ICECS 2019: 654-657 - [c95]Mateus M. Gonçalves, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Guilherme Corrêa:
Encoding Efficiency and Computational Cost Assessment of State-Of-The-Art Point Cloud Codecs. ICIP 2019: 3726-3730 - [c93]Mateus Leme, Luciano A. Braatz, Daniel Palomino, Luciano Agostini, Marcelo Schiavon Porto:
Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture. LASCAS 2019: 245-248 - [c91]Wagner Penny, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt, Leandro Soares Indrusiak:
Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms. ReCoSoC 2019: 1-8 - [c90]Wagner Penny, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt, Leandro Soares Indrusiak:
Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms. SBCCI 2019: 7 - 2018
- [c86]Wagner Penny, Mariana Ucker, Italo Machado, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt:
Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator. ICECS 2018: 237-240 - [c83]Luciano A. Braatz, Bruno Zatt, Daniel Palomino, Luciano Volcan Agostini, Marcelo Schiavon Porto:
High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design. ISCAS 2018: 1-5 - [c82]Anderson Martins, Wagner Penny, Matheus Weber, Luciano Volcan Agostini, Marcelo Schiavon Porto, Daniel Palomino, Júlio C. B. de Mattos, Bruno Zatt:
Configurable Cache Memory Architecture for Low-Energy Motion Estimation. ISCAS 2018: 1-5 - [c79]Luciano A. Braatz, Daniel Palomino, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto:
Low-Power HEVC 1-D IDCT Hardware Architecture. SBCCI 2018: 1-6 - 2017
- [c62]Anderson Martins, Wagner Penny, Matheus Weber, Daniel Palomino, Júlio C. B. de Mattos, Marcelo Schiavon Porto, Luciano Volcan Agostini, Bruno Zatt:
Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation. SBESC 2017: 31-38
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last updated on 2024-05-10 02:22 CEST by the dblp team
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