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Susmita Sur-Kolay

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Sudipta Paul 0001

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Publications

2023
[j36]
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  dblp key:
  - journals/integration/0001MBS23
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  persistent URL:
  - https://dblp.org/rec/journals/integration/0001MBS23
Sudipta Paul, Tridib Mukherjee, Pritha Banerjee, Susmita Sur-Kolay:
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. Integr. 92: 66-76 (2023)
2022
[c63]
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  dblp key:
  - conf/vlsid/SahaPBS22
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  - https://dblp.org/rec/conf/vlsid/SahaPBS22
Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Stitch-avoiding Global Routing for Multiple E-Beam Lithography. VLSID 2022: 138-143
2021
[j32]
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  - journals/iet-cds/0001BS21
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  - https://dblp.org/rec/journals/iet-cds/0001BS21
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. IET Circuits Devices Syst. 15(4): 310-329 (2021)
2019
[c57]
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  - conf/isvlsi/0001BS19
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Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. ISVLSI 2019: 212-217
2017
[c55]
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  dblp key:
  - conf/iccd/PaulBS17
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  - https://dblp.org/rec/conf/iccd/PaulBS17
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. ICCD 2017: 411-414
2015
[c48]
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  - conf/vlsi/PaulBS15
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  - https://dblp.org/rec/conf/vlsi/PaulBS15
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Flare reduction in EUV Lithography by perturbation of wire segments. VLSI-SoC 2015: 7-12

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