John M. Wilson 0002

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Liang Zhang 0038

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Publications

2009
[j4]
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Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1267-1274 (2009)
2007
[j3]
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Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 231-236 (2007)
2006
[j2]
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Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon:
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. IEEE J. Solid State Circuits 41(1): 287-296 (2006)
[c6]
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Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. CICC 2006: 265-268
[c5]
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Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Evan Erickson, Paul D. Franzon:
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver. CICC 2006: 773-776
2005
[c4]
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  - conf/islped/ZhangWBLXF05
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Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
Driver pre-emphasis techniques for on-chip global buses. ISLPED 2005: 186-191
2004
[c3]
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  - conf/glvlsi/ZhangLBWF04
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Liang Zhang, Wentai Liu, Rizwan Bashirullah, John M. Wilson, Paul D. Franzon:
Simplified delay design guidelines for on-chip global interconnects. ACM Great Lakes Symposium on VLSI 2004: 29-32

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